1. Field of the Invention
The present invention generally relates to modeling of integrated circuit layouts and more particularly to an improved process for checking for design rule (e.g., spacing) violations.
2. Description of the Related Art
Conventional integrated circuit design rule checking systems check as-designed shapes against a complicated set of rules. More recently, design rule checking systems have begun to utilize commercial programs (such as those by Numerical Technologies, Inc.333 West Maude Ave., Suite 207, Sunnyvale, Calif., U.S.A.) which model many of the diffraction induced phenomena and subsequently use the modeled wafer image as the input to a design rule checker. This approach simplifies the coding of the design rule checker since the complexities of the diffraction phenomena are accounted for in the wafer image modeling program. However, such conventional approaches do not account for photolithographic or other process effects on the net process window.
As the minimum feature size in semiconductor integrated circuit technology is pushed below the wavelength of the light used to transfer the mask images to the wafers, diffraction effects introduce the need for additional complex design rules. In addition, other physical effects such as localized etch variations, mask distortions, lens distortions, and topography related effects introduce deviations between the desired and actual printed patterns on the wafer. These effects become increasingly important as the physical dimensions of the circuit elements decrease. These complexities make it difficult both to do the design layout and the design rule checking (DRC) correctly.
FIG. 1A is a flowchart of a prior art design checking program and FIG. 1B illustrates shapes correlating to the flowchart in FIG. 1A.
Input from the design manual 10 is used to create a design data set 11 which forms the first set of shapes 16. Next, optical proximity correction and/or phase shift mask adjustment programs add notches and bars 18 or other changes to the initial set of shapes 16 to reduce the anticipated distortion which occurs during the manufacturing process to produce the shapes shown as items 17 in FIG. 1B.
A simulation program produces the wafer image 19 as shown in block 13. The simulated manufactured image 19 usually has rounded corners, and other distortions. Next a design rule check 14 is performed to determine, for example, if the space A (e.g., the space between the images 19) is within the range specified in the design rules. If the space A violates a design rule it would be flagged and identified on an errorlist 15.
The conventional approaches do not explore the effects of process variations such as focus, exposure, overlay, etc., in determining whether the shapes obey the design rules. Conventional systems utilize very complicated rule sets, have an approach limited to nominal processing quality, and do not account for real world manufacturing complications.
It is, therefore, an object of the present invention to provide a structure and method for checking semiconductor designs for design rule violations, including generating an ideal image based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
Two of the production images represent opposite manufacturing quality extremes. The production images illustrate a continuum of the potential manufacturing variations of the ideal image.
The altering of the ideal images includes accounting for mask variations and optical variations. The production images include sets of production images, each set representing a different manufacturing variation, the checking including comparing one or more of the production images within each given set to the design rules, and comparing one or more of the sets of production images to the design rules.
The potential manufacturing variations can include focus variations, dose variations, deposition variations, etching variations or alignment variations. The design rules can check feature size, spacing, intersection area, common run lengths and overlapping.
The invention produces designs which have higher yields and lower manufacturing costs by reducing design sensitivities to known manufacturing process variations. The invention enables processes to be transferred from one tool set to another which has been suitably characterized. The invention is also applicable to any computer aided design (CAD)-based design process wherein the manufacturing process variations can be modeled and the results analyzed via a set of design rules.
Further, the invention allows the designer to explore possible advantageous process variations that fall within the design rules. For example, a process variation may produced an unexpected benefits which would not have been inherently obvious from the initial unmodified design. The invention allows an unlimited number of process variations to be explored which allows the designer the opportunity to find any such unexpected benefits.